View SABC161RI-L16M_487208.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
C161RI
Preliminary 05.98 Preliminary
e/ s.d en r/ iemucto s w. nd ww ico / p:/ sem htt
C161RI Revision History: Previous Releases: Page 7 34 35, 37 41 Subjects
1998-05-01 Preliminary 1998-01 Advance Information 1997-12 Advance Information
XTAL pin numbers (MQFP) corrected.
VDDMIN corrected, special threshold parameters added (VILS, VIHS, HYS).
Specification of IIDO improved. ADCTC value in converter timing example timing corrected.
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@siemens-scg.com
Edition 1998-05-01 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
C166-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C161RI 16-Bit Microcontroller
q q q q q q q q q q q q q q q q q q q q q q q q q q q q q
C161RI
q q
High Performance 16-bit CPU with 4-Stage Pipeline 125 ns Instruction Cycle Time at 16 MHz CPU Clock 625 ns Multiplication (16 x 16 bits), 1.25 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via Prescaler or via Direct Clock Input Up to 8 MBytes Linear Address Space for Code and Data 1 KByte On-Chip Internal RAM (IRAM) 2 KBytes On-Chip Extension RAM (XRAM) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Bus 5 Programmable Chip-Select Signals 1024 Bytes On-Chip Special Function Register Area 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System, 11 External Interrupts 4-Channel 8-bit A/D Converter, conversion time down to 7.625 s 2 Multi-Functional General Purpose Timer Units with five 16-bit Timers Synchronous/Asynchronous Serial Channel (USART) High-Speed Synchronous Serial Channel I2C Bus Interface (10-bit Addressing, 400 KHz) with 2 Channels (multiplexed) Up to 76 General Purpose I/O Lines Programmable Watchdog Timer On-Chip Real Time Clock Idle and Power Down Modes with Flexible Power Management Ambient temperature range - 40 to 85 C Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstraploader 100-Pin MQFP / TQFP Package
This document describes the SAB-C161RI-LM, the SAB-C161RI-LF, the SAF-C161RI-LM and the SAB-C161RI-LF. For simplicity all versions are referred to by the term C161RI throughout this document.
Semiconductor Group
3
1998-05-01
C161RI
Introduction The C161RI is a new derivative of the Siemens C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161RI derivative is especially suited for cost sensitive applications.
VDDVSS VAREFVAGND
XTAL1 XTAL2 RSTIN RSTOUT NMI EA ALE RD WR/WRL Port 5 6 bit
PORT0 16 bit PORT1 16 bit Port 2 8 bit
C161RI
Port 3 15 bit Port 4 7 bit Port 6 8 bit
Figure 1 Logic Symbol
Ordering Information The ordering code for Siemens microcontrollers provides an exact reference to the required product. This ordering code identifies: the derivative itself, i.e. its function set the specified temperature range the package the type of delivery. For the available ordering codes for the C161RI please refer to the "Product Information Microcontrollers", which summarizes all available microcontroller variants.
q q q q
Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code.
Semiconductor Group
4
1998-05-01
C161RI
Pin Configuration MQFP Package (top view)
Figure 2
Semiconductor Group
P4.5/A21 P4.6/A22 RD WR/WRL READY ALE EA VSS VDD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VSS VDD P0H.0/AD8
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P5.2/AN2 P5.3/AN3 P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0/SCL0 P3.1/SDA0 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT VSS VDD P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0
C161RI
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NMI RSTOUT RSTIN VDD VSS P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VDD VSS P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9
5
1998-05-01
C161RI
Pin Configuration TQFP Package (top view)
P5.14/T4EUD P5.15/T2EUD VSS XTAL1 XTAL2 VDD P3.0/SCL0 P3.1/SDA0 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT VSS VDD P4.0/A16 P4.1/A17
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 VAGND VAREF P2.15/EX7IN P2.14/EX6IN P2.13/EX5IN P2.12/EX4IN P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/SDA2 P6.6/SCL1 P6.5/SDA1 P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
C161RI
VDD VSS P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VDD VSS P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11
Figure 3
Semiconductor Group
P4.2/A18 P4.3/A19 P4.4/A20 P4.5/A21 P4.6/A22 RD WR/WRL READY ALE EA VSS VDD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VSS VDD P0H.0/AD8 P0H.1/AD9 P0H.2/AD10
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
6
1998-05-01
C161RI
Pin Definitions and Functions Symbol P5.0 - P5.3, P5.14 - P5.15 Pin No. Pin No. Input Function TQFP MQFP Outp 97 - 100, 1- 2 99 - 2, 3- 4 I I I I Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as the (up to 4) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x, x=0...3). The following pins of Port 5 also serve as timer inputs: P5.14 T4EUD GPT1 Timer T4 Ext.Up/Down Ctrl.Input P5.15 T2EUD GPT1 Timer T5 Ext.Up/Down Ctrl.Input Input to the oscillator amplifier and input to the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 3 pins also serve for alternate functions: P3.0 SCL0 I2C Bus Clock Line 0 P3.1 SDA0 I2C Bus Data Line 0 P3.2 CAPIN GPT2 Register CAPREL Capture Input P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output P3.4 T3EUD GPT1 Timer T3 Ext.Up/Dwn Ctrl.Input P3.5 T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture P3.6 T3IN GPT1 Timer T3 Count/Gate Input P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture P3.8 MRST SSC Master-Rec./Slave-Transmit I/O P3.9 MTSR SSC Master-Transmit/Slave-Rec. O/I P3.10 TxD0 ASC0 Clock/Data Output (Asyn./Syn.) P3.11 RxD0 ASC0 Data Input (Asyn.) or I/O (Syn.) Ext. Memory High Byte Enable Signal, P3.12 BHE WRH Ext. Memory High Byte Write Strobe P3.13 SCLK SSC Master Clock Outp./Slave Cl. Inp. P3.15 CLKOUT System Clock Output (=CPU Clock) Note: Pins P3.0 and P3.1 are open drain outputs only. XTAL1:
XTAL1 XTAL2
4 5
6 7
I O
P3.0 - P3.13, P3.15
7- 20, 21
9- 22, 23
I/O I/O I/O
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
I/O I/O I O I I I I I/O I/O O I/O O O I/O O
Semiconductor Group
7
1998-05-01
C161RI
Pin Definitions and Functions (cont'd) Symbol P4.0 - P4.6 Pin No. Pin No. Input Function TQFP MQFP Outp 24 - 30 26 32 I/O I/O Port 4 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.6 A22 Most Significant Segment Addr. Line External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C161RI to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The C161RI must have this pin tied to `0'. Note: This pin is expected to be used to accept the programming voltage for OTP versions of the C161RI.
24 ... 30 RD 31
26 ... 32 33 34
O ... O O O
WR/WRL 32
READY
33
35
I
ALE
34
36
O
EA
35
37
I
Semiconductor Group
8
1998-05-01
C161RI
Pin Definitions and Functions (cont'd) Symbol PORT0: P0L.0 - P0L.7, P0H.0 P0H.7 Pin No. Pin No. Input Function TQFP MQFP Outp I/O 38 - 45, 48 - 55 40 - 47, 50 - 57 PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of external bus configurations, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the C161RI. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon a software reset, a WDT reset and a hardware reset. 1) Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161RI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally.
PORT1: P1L.0 - P1L.7, P1H.0 P1H.7
I/O 56 - 63, 66 - 73 58 65, 68 75
RSTIN
76
78
I
RSTOUT 77
79
O
NMI
78
80
I
Semiconductor Group
9
1998-05-01
C161RI
Pin Definitions and Functions (cont'd) Symbol P6.0 - P6.7 Pin No. Pin No. Input Function TQFP MQFP Outp 79 - 86 81 - 88 I/O I/O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The Port 6 pins also serve for alternate functions: Chip Select 0 Output P6.0 CS0 ... ... ... Chip Select 4 Output P6.4 CS4 P6.5 SDA1 I2C Bus Data Line 1 P6.6 SCL1 I2C Bus Clock Line 1 P6.7 SDA2 I2C Bus Data Line 2 Note: Pins P6.5-P6.7 are open drain outputs only. Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 2 pins also serve for alternate functions: P2.8 EX0IN Fast External Interrupt 0 Input ... ... ... P2.15 EX7IN Fast External Interrupt 7 Input Reference voltage for the A/D converter. Reference ground for the A/D converter. Digital Supply Voltage: + 5 V during normal operation and idle mode. 2.5 V during power down mode Digital Ground.
79 ... 83 84 85 86 P2.8 - P2.15 87 - 94
81 ... 85 86 87 88 89 - 96
O ... O I/O I/O I/O I/O I/O
87 ... 94
89 ... 96 97 98
I ... I -
VAREF VAGND VDD
95 96
6, 23, 8, 25, 37, 47, 39, 49, 65, 75 67, 77 3, 22, 5, 24, 36, 46, 38, 48, 64, 74 66, 76
VSS
1) The
following behavior differences must be observed when the bidirectional reset is active:
Bit BDRSTEN in register SYSCON cannot be changed after EINIT. After a reset bit BDRSTEN is cleared. The reset indication flags always indicate a long hardware reset. The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low. q Pin RSTIN may only be connected to external reset devices with an open drain output driver. q A short hardware reset is extended to the duration of the internal reset sequence.
q q q q
Semiconductor Group
10
1998-05-01
C161RI
Functional Description The C161RI is a low cost downgrade of the high performance microcontroller C167CR with OTP or internal ROM, reduced peripheral functionality and a high performance Capture Compare Unit with an additional functionality. The architecture of the C161RI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161RI. Note: All time specifications refer to a CPU clock of 16 MHz (see definition in the AC Characteristics section).
vrhy SPH
D9hh
&&RUH
&38 &RUH &38
%
% 9hh % 9hh
Q A y h 9
Drhy S6H AF7r
APT8
v)A %HC0
YU6G
rphyr AqvrpAqvr
@rhyAD9hh
r r q q 6 A A h h 9 A
3(&
A ArADS Xhpuqt
%
,QWHUUXSW &RQWUROOHU
QrvurhyA9hh
D87 Drshpr YS6H !AF7r
DrA7
%
Y V H A I P I A v i % A
' % A Q % A Q &
@rhy 7 HVY yAE Y7VT 8y 8TAGtvp #A8T
# 8uhry 'iv 698
VT6SU
Tp 8uhry TQD
BQUA
BQUA!
SU8
6 8 % ;
UA! UA" UA#
UA$ UA%
6T8 7SB
TT8 7SB
QA#
QA
QA$
QA"
QA!
8 % SDAAW
%
%
$
'
Figure 4 Block Diagram
Semiconductor Group
11
1998-05-01
C161RI
Memory Organization The memory space of the C161RI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. 1 KByte of on-chip Internal RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller.
Semiconductor Group
12
1998-05-01
C161RI
External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultiplexed - 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed - 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed - 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported via a particular `Ready' function. For applications which require less than 8 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lines at all. It outputs all 7 address lines, if an address space of 8 MBytes is used.
Semiconductor Group
13
1998-05-01
C161RI
Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161RI's instructions can be executed in just one machine cycle which requires 125 ns at 16 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU SP STKOV STKUN Exec. Unit Instr. Ptr. Instr. Reg. 32 ROM 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr. MDH MDL Mul/Div-HW Bit-Mask Gen ALU (16-bit) Barrel - Shifter Context Ptr. ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 Registers
16 Internal RAM R15
General Purpose
R15
R0
16
MCB02147
Figure 5 CPU Block Diagram
Semiconductor Group
14
1998-05-01
C161RI
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161RI instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Semiconductor Group
15
1998-05-01
C161RI
Interrupt System With an interrupt response time within a range from just 315 ns to 750 ns (in case of internal program execution), the C161RI is capable of reacting very fast to the occurrence of nondeterministic events. The architecture of the C161RI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161RI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number.
Semiconductor Group
16
1998-05-01
C161RI
The following table shows all of the possible C161RI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error I C Data Transfer Event I2C Protocol Event X-Peripheral Node 2 PLL Unlock / RTC
2
Request Flag CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR T2IR T3IR T4IR T5IR T6IR CRIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR XP0IR XP1IR XP2IR XP3IR
Enable Flag CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE XP0IE XP1IE XP2IE XP3IE
Interrupt Vector CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT XP0INT XP1INT XP2INT XP3INT
Vector Location 00'0060H 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'0100H 00'0104H 00'0108H 00'010CH
Trap Number 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 22H 23H 24H 25H 26H 27H 28H 29H 2AH 47H 2BH 2CH 2DH 2EH 2FH 40H 41H 42H 43H
A/D Conversion Complete ADCIR
Semiconductor Group
17
1998-05-01
C161RI
The C161RI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during runtime: Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction NMI STKOF STKUF UNDOPC PRTFLT ILLOPA ILLINA ILLBUS Trap Flag Trap Vector RESET RESET RESET Vector Location 00'0000H 00'0000H 00'0000H Trap Number 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH Trap Priority III III III II II II I I I I I
NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H
[2CH - 3CH] [0BH - 0FH] Any [00'0000H - 00'01FCH] in steps of 4H Any [00H - 7FH] Current CPU Priority
Semiconductor Group
18
1998-05-01
C161RI
General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 500 ns (@ 16 MHz CPU clock). The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/ underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. With its maximum resolution of 250 ns (@ 16 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin
Semiconductor Group
19
1998-05-01
C161RI
(CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.
T2EUD CPU Clock T2IN
n
U/D GPT1 Timer T2 2 n = 3...10 T2 Mode Control Reload Capture Interrupt Request
CPU Clock
2 n = 3...10
n
T3IN T3EUD
T3 Mode Control U/D
Toggle FF GPT1 Timer T3 T3OTL
Capture T4IN CPU Clock 2 n = 3...10 GPT1 Timer T4 T4EUD U/D
n
T4 Mode Control
Reload
Interrupt Request
Interrupt Request
MCB02141
Figure 6 Block Diagram of GPT1
Semiconductor Group
20
1998-05-01
C161RI
CPU Clock
2n n=2...9
T5 Mode Control Clear Capture
GPT2 Timer T5
Interrupt Request
CAPIN GPT2 CAPREL
Interrupt Request
Interrupt Request CPU Clock 2n n=2...9 T6 Mode Control GPT2 Timer T6 T6OTL
Figure 7 Block Diagram of GPT2
Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 31 s and 525 ms can be monitored (@ 16 MHz). The default Watchdog Timer interval after reset is 8.2 ms (@ 16 MHz).
Semiconductor Group
21
1998-05-01
C161RI
Real Time Clock The Real Time Clock (RTC) module of the C161RI consists of a chain of 3 divider blocks, a fixed 8-bit divider, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver and is therefore independent from the selected clock generation mode of the C161RI. All timers count up. The RTC module can be used for different purposes:
q System clock to determine the current time and date q Cyclic time based interrupt q 48-bit timer for long term measurements
T14REL
Reload
T14
8:1
fRTC
Interrupt Request
RTCL
RTCL
Figure 7-1 RTC Block Diagram Note: The registers associated with the RTC are not effected by a reset in order to maintain the correct system time even when intermediate resets are executed.
Semiconductor Group
22
1998-05-01
C161RI
A/D Converter For analog signal measurement, an 8-bit A/D converter with 4 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 4 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C161RI supports two different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. The 8-bit result can be left-aligned or right-aligned within a 10-bit result area. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer.
I2C Module The integrated I2C Bus Module handles the transmission and reception of frames over the two-line I2C bus in accordance with the I2C Bus specification. The on-chip I2C Module can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or in multi-master mode. Several physical interfaces (port pins) can be established under software control. Data can be transferred at speeds up to 400 Kbit/sec. Two interrupt nodes dedicated to the I2C module allow efficient interrupt service and also support operation via PEC transfers. Note: The port pins associated with the I2C interfaces feature open drain drivers only, as required by the I2C specification.
Semiconductor Group
23
1998-05-01
C161RI
Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 500 KBaud and half-duplex synchronous communication at up to 2 MBaud @ 16 MHz CPU clock. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 4 Mbaud @ 16 MHz CPU clock. It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2...16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.
Semiconductor Group
24
1998-05-01
C161RI
Parallel Ports The C161RI provides up to 76 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The other IO ports operate in push/pull mode, except for the I2C interface pins which are open drain pins only. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A22/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. Port 6 provides the optional chip select signals and interface lines for the I2C module. All port lines that are not used for these alternate functions may be used as general purpose IO lines.
Semiconductor Group
25
1998-05-01
C161RI
Instruction Set Summary The table below lists the instructions of the C161RI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C166 Family Instruction Set Manual". This document also provides a detailed description of each instruction.
Instruction Set Summary Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2
Semiconductor Group
26
1998-05-01
C161RI
Instruction Set Summary (cont'd) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Semiconductor Group
27
1998-05-01
C161RI
Special Function Registers Overview The following table lists all SFRs which are implemented in the C161RI in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-Peripherals (I2C) are marked with the letter "X" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
Name ADCIC ADCON ADDAT ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC
Physical 8-Bit Address Address b FF98H b FFA0H FEA0H FE18H FE1AH FE1CH FE1EH b FF9AH CCH D0H 50H 0CH 0DH 0EH 0FH CDH 86H 8AH 8BH 8CH 8DH 25H C4H C5H C6H C7H C8H C9H CAH CBH 08H
Description A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register External Interrupt 0 Control Register External Interrupt 1 Control Register External Interrupt 2 Control Register External Interrupt 3 Control Register External Interrupt 4 Control Register External Interrupt 5 Control Register External Interrupt 6 Control Register External Interrupt 7 Control Register CPU Context Pointer Register
Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H
BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH CAPREL CC8IC CC9IC CC10IC CC11IC CC12IC CC13IC CC14IC CC15IC CP FE4AH b FF88H b FF8AH b FF8CH b FF8EH b FF90H b FF92H b FF94H b FF96H FE10H
Semiconductor Group
28
1998-05-01
C161RI
Name CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DPP0 DPP1 DPP2 DPP3 EXICON ICADR ICCFG ICCON ICRTB ICST IDCHIP IDMANUF IDMEM IDPROG ISNC MDC MDH MDL ODP2 ODP3 ODP6 ONES
Physical 8-Bit Address Address b FF6AH FE08H B5H 04H
Description GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (8 bits, not directly writeable) P0L Direction Control Register P0H Direction Control Register P1L Direction Control Register P1H Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) External Interrupt Control Register I2C Address Register I2C Configuration Register I2C Control Register I2C Receive/Transmit Buffer I2C Status Register Identifier Identifier Identifier Identifier Interrupt Subnode Control Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Constant Value 1's Register (read only)
Reset Value 0000H 0000H 00H 00H 00H 00H 0000H 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 0XXXH XX00H 0000H XXH 0000H 09XXH 1820H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00H FFFFH
b F100H E 80H b F102H E 81H b F104H E 82H b F106H E 83H b FFC2H b FFC6H b FFCAH b FFCEH FE00H FE02H FE04H FE06H E1H E3H E5H E7H 00H 01H 02H 03H
b F1C0H E E0H ED06H X --ED00H X --ED02H X --ED08H X --ED04H X --F07CH E 3EH F07EH E 3FH F07AH E 3DH F078H E 3CH b F1DEH E EFH b FF0EH FE0CH FE0EH 87H 06H 07H
b F1C2H E E1H b F1C6H E E3H b F1CEH E E7H b FF1EH 8FH
Semiconductor Group
29
1998-05-01
C161RI
Name P0L P0H P1L P1H P2 P3 P4 P5 P5DIDIS P6 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PSW RP0H RTCH RTCL S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF
Physical 8-Bit Address Address b FF00H b FF02H b FF04H b FF06H b FFC0H b FFC4H b FFC8H b FFA2H b FFA4H b FFCCH FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b FF10H 80H 81H 82H 83H E0H E2H E4H D1H D2H E6H 60H 61H 62H 63H 64H 65H 66H 67H 88H
Description Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register Port 3 Register Port 4 Register (7 bits) Port 5 Register (read only) Port 5 Digital Input Disable Register Port 6 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register CPU Program Status Word System Startup Configuration Register (Rd. only) RTC High Register RTC Low Register Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register
Reset Value 00H 00H 00H 00H 0000H 0000H 00H XXXXH 0000H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH no no 0000H 0000H 0000H XXXXH 0000H 0000H 0000H
b F108H E 84H F0D6H E 6BH F0D4H E 6AH FEB4H b FFB0H b FF70H FEB2H b FF6EH 5AH D8H B8H 59H B7H
b F19CH E CEH FEB0H 58H
Semiconductor Group
30
1998-05-01
C161RI
Name S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON
Physical 8-Bit Address Address b FF6CH FE12H b FFB2H b FF76H b FF74H b FF72H FE14H FE16H b FF12H B6H 09H D9H BBH BAH B9H 0AH 0BH 89H
Description Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CPU System Configuration Register 2 CPU System Configuration Register 3 RTC Timer 14 Register RTC Timer 14 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register
Reset Value 0000H FC00H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H 0XX0H1) 0000H 0000H no no 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
F0B4H E 5AH
F0B2H E 59H F0B0H E 58H
SYSCON2 b F1D0H E E8H SYSCON3 b F1D4H E EAH T14 T14REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR F0D2H E 69H F0D0H E 68H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H b FF66H FE48H b FF48H b FF68H b FFACH 20H A0H B0H 21H A1H B1H 22H A2H B2H 23H A3H B3H 24H A4H B4H D6H
Semiconductor Group
31
1998-05-01
C161RI
Name WDT XP0IC XP1IC XP2IC XP3IC ZEROS
1) 2)
Physical 8-Bit Address Address FEAEH 57H D7H
Description Watchdog Timer Register (read only) Watchdog Timer Control Register I2C Data Interrupt Control Register I2C Protocol Interrupt Control Register X-Peripheral 2 Interrupt Control Register RTC Interrupt Control Register Constant Value 0's Register (read only)
Reset Value 0000H 00XXH2) 0000H 0000H 0000H 0000H 0000H
WDTCON b FFAEH
b F186H E C3H b F18EH E C7H b F196H E CBH b F19EH E CFH b FF1CH 8EH
The system configuration is selected during reset. The reset value depends on the indicated reset source.
Semiconductor Group
32
1998-05-01
C161RI
Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C161RI ...................................................................................................................0 to + 70 C SAF-C161RI ..............................................................................................................- 40 to + 85 C Storage temperature (TST)........................................................................................- 65 to + 150 C Voltage on VDD pins with respect to ground (VSS) ..................................................... - 0.5 to + 6.5 V Voltage on any pin with respect to ground (VSS) .................................................- 0.5 to VDD + 0.5 V Input current on any pin during overload condition.................................................. - 10 to + 10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161RI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C161RI will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161RI.
Semiconductor Group
33
1998-05-01
C161RI
DC Characteristics
VDD = 4.5 - 5.5 V; VSS = 0 V; fCPU = 20 MHz TA = 0 to + 70 C for SAB-C161RI TA = - 40 to + 85 C for SAF-C161RI
Parameter Input low voltage (P3.0, P3.1, P6.5, P6.6, P6.7) Input low voltage (TTL) Input low voltage (Special Threshold) Input high voltage RSTIN Input high voltage XTAL1, P3.0, P3.1, P6.5, P6.6, P6.7 Input high voltage (TTL) Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Symbol min. Limit Values max. 0.3 VDD 0.2 VDD - 0.1 2.0 V V V V V V V mV V - - - - - - - - - 0.5 - 0.5 - 0.5 0.6 VDD 0.7 VDD 0.2 VDD + 0.9 0.8 VDD - 0.2 400
CC
Unit
Test Condition
VIL1 VIL VILS VIH1 VIH2 VIH VIHS HYS
SR
SR
SR
SR SR
VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5
- 0.45
SR
SR
Output low voltage VOL (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (P3.0, P3.1, P6.5, P6.6, P6.7) Output low voltage (all other outputs)
-
IOL = 2.4 mA
VOL2 VOL1
CC
- - 0.9 VDD 2.4 0.9 VDD 2.4 - - - 50 - - 500
0.4 0.45 -
V V V
IOL2 = 3 mA IOL1 = 1.6 mA IOH = - 500 A IOH = - 2.4 mA IOH = - 250 A IOH = - 1.6 mA
0.45 V < VIN < VDD 0.45 V < VIN < VDD
5) 8)
CC
Output high voltage VOH (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs)
1)
CC
VOH1 IOZ1 IOZ2 IOV RRST
4)
CC
- 200 500 5 250 - 40 -
V V nA nA mA k A A
Input leakage current (Port 5) Input leakage current (all other) Overload current RSTIN pullup resistor Read/Write inactive current Read/Write active current
4)
CC CC SR CC
-
IRWH IRWL
2) 3)
VOUT = 2.4 V VOUT = VOLmax
1998-05-01
Semiconductor Group
34
C161RI
Parameter ALE inactive current ALE active current
4) 4) 4)
Symbol min.
Limit Values max. 40 - - 40 - - 10 - 20 10 7+ 3 x fCPU 3+ 1.1 x fCPU - 500 - - 500 - - 100 - - - - -
Unit A A A A A A A pF mA mA
Test Condition
IALEL IALEH IP6H IP6L
4)
2) 3) 2) 3) 2) 3)
CC CC
VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax
0 V < VIN < VDD
Port 6 inactive current Port 6 active current
4)
PORT0 configuration current XTAL1 input current Pin capacitance 5) (digital inputs/outputs) Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active
IP0H IP0L IIL CIO IDD IIDX IIDO
f = 1 MHz TA = 25 C
RSTIN = VIL2 fCPU in [MHz] 6) RSTIN = VIH1 fCPU in [MHz] 6) RSTIN = VIH1 fOSC in [MHz] 6)
Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Power-down mode supply current with RTC running Power-down mode supply current with RTC disabled
500 + A 50 x fOSC 9) 100 + A 9) 25 x fOSC 50 A
IPDR IPDO
- -
VDD = 5.5 V fOSC in [MHz] 7) VDD = 5.5 V 7)
Semiconductor Group
35
1998-05-01
C161RI
Notes
1)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Adapt-mode. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VDDmax and 20 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The oscillator also contributes to the total supply current. The given values refer to the worst case, i.e. IPDRmax. For lower oscillator frequencies the respective supply current can be reduced accordingly. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage (VDD and VSS) must remain within the specified limits. This parameter is determined mainly by the current consumed by the oscillator. This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given for IPDR refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. A typical value for IPDR at room temperature and fCPU = 16 MHz is 300 A.
2) 3) 4) 5) 6)
7)
8)
9)
Semiconductor Group
36
1998-05-01
C161RI
I [mA]
IDDmax
70 IDDtyp
40 IIDXmax IIDXtyp 10
5
10
15
20
fCPU [MHz]
Figure 8 Supply/Idle Current as a Function of Operating Frequency I [A] 1500 1250 1000 IIDOtyp 750 500 250 IPDOmax 4 8 12 16 fOSC [MHz] IPDRmax
IIDOmax
Figure 9 Power Down Supply Current as a Function of Oscillator Frequency
Semiconductor Group
37
1998-05-01
C161RI
AC Characteristics Definition of Internal Timing The internal operation of the C161RI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below).
Direct Clock Drive fXTAL fCPU
TCL TCL
Prescaler Operation fXTAL fCPU
TCL TCL
Figure 10 Generation Mechanisms for the CPU Clock The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C161RI. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5).
Semiconductor Group
38
1998-05-01
C161RI
The table below associates the combinations of these three bits with the respective clock generation mode. C161RI Clock Generation Modes P0.15-13 (P0H.7-5) 1 1 1 1 0 0 0 0
1)
CPU Frequency fCPU = Notes fXTAL x F Reserved Reserved Reserved Reserved Default configuration without pull-downs
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
fXTAL x 1
Reserved
Direct drive 1) CPU clock via prescaler
fXTAL / 2
Reserved
The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation When pins P0.15-13 (P0H.7-5) equal `001' during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Direct Drive When pins P0.15-13 (P0H.7-5) equal `011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fXTAL x DCmin (DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL. Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin.
Semiconductor Group
39
1998-05-01
C161RI
AC Characteristics External Clock Drive XTAL1
VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 C for SAB-C161RI TA = - 40 to + 85 C for SAF-C161RI
Parameter Oscillator period High time Low time Rise time Fall time
1) 2)
Symbol min.
Direct Drive 1:1 max. 8000 - - 10
1) 1) 2)
Prescaler 2:1 min. 31 6 6 - - max. 4000 - - 6
1)
Unit ns ns ns ns ns
tOSC t1 t2 t3 t4
SR SR SR SR SR
62 25 1) 2) 25 - -
10 1)
6 1)
The clock input signal must reach the defined levels VIL and VIH2. The specified minimum low and high times allow a duty cycle range of 40...60% at 16 MHz.
t1
0.5 VDD
t3
t4 VIH2 VIL
t2 t OSC
MCT02534
Figure 11 External Clock Drive XTAL1
Semiconductor Group
40
1998-05-01
C161RI
A/D Converter Characteristics
VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 C for SAB-C161RI TA = - 40 to + 85 C for SAF-C161RI 4.0 V VAREF VDD + 0.1 V; VSS - 0.1 V VAGND VSS + 0.2 V
Parameter Analog input voltage range Basic clock frequency Sample time Conversion time Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Symbol Limit Values min. max. Unit V MHz Test Condition
1) 2)
VAIN SR VAGND fBC tS tC
0.5 CC - CC -
VAREF
4 6 tBC 30 tBC + 2 tCPU 2
tBC = 1 / fBC
3)
tCPU = 1 / fCPU
LSB k k pF
4)
TUE CC -
RAREF SR - RASRC SR - CAIN CC -
tBC / 125
- 0.25
tBC in [ns] 5) 6) tS in [ns] 6) 7)
6)
tS / 750
- 0.25 50
The conversion time of the C161RI's A/D Converter is programmable. The table below should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. ADCON.15|14 A/D Converter Basic Clock (ADCTC) fBC 2) 00 01 10 11
fCPU / 2 fCPU / 4 fCPU / 8 fCPU / 16
Converter Timing Example: Assumptions:
fCPU = 16 MHz (i.e. tCPU = 62.5 ns), ADCTC = `01'.
= fCPU / 4 = 4 MHz, i.e. tBC = 250 ns. = tBC x 6 = 1500 ns. = 30 tBC + 2 tCPU = (7500 + 125) ns = 7.625 s.
Basic clock fBC Sample time tS Conversion time tC
Semiconductor Group
41
1998-05-01
C161RI
Notes
1)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively.
The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from the table above. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, guaranteed by design. During the sample time the input capacitance CI can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from the table above.
2) 3)
4)
5)
6) 7)
Semiconductor Group
42
1998-05-01
C161RI
Testing Waveforms
AC inputs during testing are driven at 2.4 V for a logic `1' and 0.45 V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 12 Input Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA). Figure 13 Float Waveforms
Semiconductor Group
43
1998-05-01
C161RI
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values TCL x 2TCL x (15 - ) 2TCL x (1 - )
tA tC tF
AC Characteristics Multiplexed Bus
VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 C for SAB-C161RI TA = - 40 to + 85 C for SAF-C161RI CL = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (186 ns at 16 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock = 16 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) max. - - - - - 6 37 - - 21 + tA 15 + tA 21 + tA 21 + tA - 10 + tA - - 53 + tC 84 + tC Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 16 + tA - TCL - 10 + tA - TCL - 10 + tA - - 10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - 6 TCL + 6 - - Unit
t5 t6 t7 t8 t9 t10 t11 t12 t13
CC CC CC CC CC CC CC CC CC
Semiconductor Group
44
1998-05-01
C161RI
Parameter
Symbol
Max. CPU Clock = 16 MHz min. max. 43 + tC 74 + tC 74 + tA + tC 95 + 2tA + tC - 49 + tF - - - - 10 - tA 74 + tC + 2tA - - - 0 31 39 + tC - - - - 0 - 43 + tC 49 + tF 49 + tF 49 + tF - 4 - tA - 80 + tF 27 + tA - 4 + tA - - - - - - - 0 -
Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 24 + tC
Unit
RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay)
t14 t15 t16 t17 t18 t19 t22 t23 t25 t27 t38 t39 t40 t42 t43 t44 t45 t46
SR SR SR SR SR SR CC CC CC CC CC SR CC CC CC CC CC SR
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF - 4 - tA - 3TCL - 14 + tF TCL - 4 + tA -4 + tA - - -
Semiconductor Group
45
1998-05-01
C161RI
Parameter
Symbol
Max. CPU Clock = 16 MHz min. max. 70 + tC - - - - 43 + tF - - - 53 + tC 84 + tC 49 + tC 0 - 43 + tF 43 + tF -
Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. 3TCL - 24 + tC - - - - 2TCL - 20 + tF - -
Unit
RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
t47 t48 t49 t50 t51 t52 t54 t56
SR CC CC CC SR SR CC CC
ns ns ns ns ns ns ns ns
2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF
Semiconductor Group
46
1998-05-01
C161RI
t5
ALE
t16
t25
t38
CSx
t39
t40
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS
t7 t18
Address
t54 t19
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address
t23
Data Out
t8
WR, WRL, WRH
t10
t56 t22 t12 t50 t48
t42
WrCSx
t44
Figure 14-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group
47
1998-05-01
C161RI
t5
ALE
t16 t38 t39
t25
t40
CSx
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS Address
t7 t18
t54 t19
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address
t23
Data Out
t8
WR, WRL, WRH
t10
t56 t22 t12 t50 t48
t42
WrCSx
t44
Figure 14-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group
48
1998-05-01
C161RI
t5
ALE
t16
t25
t38
CSx
t39
t40
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS
t7 t18
Address
t54 t19
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23
t9
WR, WRL, WRH
t56 t11 t22 t13 t45 t50 t49
t43
WrCSx
Figure 14-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group
49
1998-05-01
C161RI
t5
ALE
t16 t38 t39
t25
t40
CSx
A23-A16 (A15-A8) BHE
t17
Address
t27
t6
Read Cycle BUS Address
t7 t18
t54 t19
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23
t56 t9
WR, WRL, WRH
t11 t13
t22
t43
WrCSx
t45 t49
t50
Figure 14-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group
50
1998-05-01
C161RI
AC Characteristics Demultiplexed Bus
VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 C for SAB-C161RI TA = - 40 to + 85 C for SAF-C161RI CL = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (125 ns at 16 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock = 16 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR Data hold after WR ALE rising edge after RD, WR max. - - - - - - 43 + tC 74 + tC 74 + tA + tC 95 + 2tA + tC - 49 + 2tA + tF 1) 21 + 2tA + tF 1) - - - 21 + tA 15 + tA 21 + tA - 10 + tA 53 + tC 84 + tC - - - - 0 - - 43 + tC 21 + tF - 10 + tF Variable CPU Clock 1/2TCL = 1 to 16 MHz min. max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TCL - 10 + tA - TCL - 16 + tA - TCL - 10 + tA - 10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL - 20 + tC - 10 + tF - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + 2tA + tF 1) TCL - 10 + 2tA + tF 1) - Unit
t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 t26
CC CC CC CC CC CC SR SR SR SR SR SR SR CC CC CC
TCL - 10 + tF - -
Semiconductor Group
51
1998-05-01
C161RI
Parameter
Symbol
Max. CPU Clock = 16 MHz min. max. - 10 - tA 74 + tC + 2tA - - - 39 + tC 70 + tC - - - - 43 + tF 11 + tF - - 0 + tF - 4 - tA - 17 + tF 27 + tA - 4 + tA - - 53 + tC 84 + tC 49 + tC 0 - - - 10 + tF 17 + tF
Variable CPU Clock 1/2TCL = 1 to 16 MHz min. 0 + tF - 4 - tA - TCL - 14 + tF TCL - 4 + tA -4 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - - - 10 + tF TCL - 14 + tF max. - 10 - tA 3TCL - 20 + tC + 2tA - - - 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - -
Unit
Address hold after WR ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR
2)
t28 t38 t39 t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
CC CC SR CC CC CC SR SR CC CC CC SR SR SR CC CC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS
1) 2)
RW-delay and tA refer to the next following bus cycle. It is guaranteed by design that read data are latched before the address changes.
Semiconductor Group
52
1998-05-01
C161RI
t5
ALE
t16
t26
t38
CSx
t39
t41
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t20 t18
Data In
t8
RD
t14 t12
t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 15-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group
53
1998-05-01
C161RI
t5
ALE
t16 t38 t39
t26
t41
CSx
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t20 t18
Data In
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t12 t42 t50 t48 t22
WrCSx
Figure 15-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group
54
1998-05-01
C161RI
t5
ALE
t16
t26
t38
CSx
t39
t41
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t21 t18
Data In
t9
RD
t15 t43 t13 t47 t49 t51 t68
RdCSx
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t9
WR, WRL, WRH
t57 t22 t13 t50 t49
t43
WrCSx
Figure 15-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group
55
1998-05-01
C161RI
t5
ALE
t16 t38 t39
t26
t41
CSx
A23-A16 A15-A0 BHE
t17
Address
t28
t6
Read Cycle BUS (D15-D8) D7-D0
t55 t21 t18
Data In
t9
RD
t15 t13 t51 t68
t43
RdCSx
t47 t49
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t57 t9 t22 t13 t43 t50 t49
WR, WRL, WRH
WrCSx
Figure 15-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group
56
1998-05-01
C161RI
AC Characteristics CLKOUT and READY
VDD = 4.5 - 5.5 V; VSS = 0 V TA = 0 to + 70 C for SAB-C161RI TA = - 40 to + 85 C for SAF-C161RI CL = 100 pF
Parameter Symbol Max. CPU Clock = 16 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 62 - - 4 4 10 + tA - - - - - 1 + 2tA + tC + tF 2) 62 25 21 - - 0 + tA 14 4 76 14 4 0 Variable CPU Clock 1/2TCL = 1 to 16 MHz min. 2TCL TCL - 6 TCL - 10 - - 0 + tA 14 4 2TCL + 14 14 4 0 max. 2TCL - - 4 4 10 + tA - - - - - ns ns ns ns ns ns ns ns ns ns ns Unit
t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60
CC CC CC CC CC CC SR SR SR SR SR SR
TCL - 30 ns + 2tA + tC + tF
2)
Notes
1) 2)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
Semiconductor Group
57
1998-05-01
C161RI
Running cycle 1)
READY waitstate
MUX/Tristate 6)
CLKOUT
t32 t30 t34
t33 t31 t29
ALE
7)
Command RD, WR
2)
t35
Sync READY
3)
t36
t35
3)
t36
t58
Async READY
3)
t59
t58
3) 5)
t59
t60 4)
t37
see
6)
Figure 16 CLKOUT and READY
Notes
1) 2) 3)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note 4)). Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here.
4)
5)
6)
7)
Semiconductor Group
58
1998-05-01
C161RI
Package Outlines
Plastic Package, P-MQFP-100-2 (SMD) (Plastic Metric Quad Flat Package)
Figure 17
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 59
Dimensions in mm 1998-05-01
C161RI
Package Outlines (cont'd)
Plastic Package, P-TQFP-100-1 (SMD) (Plastic Thin Metric Quad Flat Package)
Figure 18
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 60
Dimensions in mm 1998-05-01

▲Up To Search▲

Price & Availability of SABC161RI-L16M

	To Download SABC161RI-L16M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .